Xilinx virtex-5 fpga User Manual

338 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 7: SelectIO Logic Resources
IDELAYCTRL Primitive
Figure 7-15 shows the IDELAYCTRL primitive.
IDELAYCTRL Ports
RST - Reset
The reset input pin (RST) is an active-High asynchronous reset. IDELAYCTRL must be
reset after configuration (and the REFCLK signal has stabilized) to ensure proper
IODELAY operation. A reset pulse width T
IDELAYCTRL_RPW
is required. IDELAYCTRL
must be reset after configuration.
REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all
IODELAY modules in the same region. This clock must be driven by a global clock buffer
(BUFGCTRL). REFCLK must be F
IDELAYCTRL_REF
± the specified ppm tolerance
(IDELAYCTRL_REF_PRECISION) to guarantee a specified IODELAY resolution
(T
IDELAYRESOLUTION
). REFCLK can be supplied directly from a user-supplied source, the
PLL, or from the DCM, and must be routed on a global clock buffer.
RDY - Ready
The ready (RDY) signal indicates when the IODELAY modules in the specific region are
calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock
period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The
implementation tools allow RDY to be unconnected/ignored. Figure 7-16 illustrates the
timing relationship between RDY and RST.
X-Ref Target - Figure 7-15
Figure 7-15: IDELAYCTRL Primitive
REFCLK RDY
RST
IDELAYCTRL
ug190_7_10_041206

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English