Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 243
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Table 6-8 details the allowed attributes that can be applied to the LVCMOS12 I/O
standard.
LVDCI (Low Voltage Digitally Controlled Impedance)
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as LVTTL,
LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of
the driven line. Virtex-5 devices provide a controlled impedance output driver to provide
series termination without external source termination resistors. The impedance is set by
the common external reference resistors, with resistance equal to the trace characteristic
impedance, Z
0
.
Sample circuits illustrating both unidirectional and bidirectional termination techniques
for a controlled impedance driver are shown in Figure 6-31 and Figure 6-32. The DCI I/O
standards supporting a controlled impedance driver are: LVDCI_15, LVDCI_18,
LVDCI_25, and LVDCI_33.
Table 6-8: Allowed Attributes for the LVCMOS12 I/O Standard
Attributes
Primitives
IBUF/IBUFG OBUF/OBUFT IOBUF
IOSTANDARD LVCMOS12 LVCMOS12 LVCMOS12
DRIVE UNUSED 2, 4, 6, 8 2, 4, 6, 8
SLEW UNUSED {FAST, SLOW} {FAST, SLOW}
X-Ref Target - Figure 6-31
Figure 6-31: Controlled Impedance Driver with Unidirectional Termination
X-Ref Target - Figure 6-32
Figure 6-32: Controlled Impedance Driver with Bidirectional Termination
Z
0
IOB
IOB
LVDCI
LVDCI
ug190_6_28_022806
R
0
= R
VRN
= R
VRP
= Z
0
Z
0
IOB
IOB
LVDCI
LVDCI
ug190_6_29_022806
R
0
= R
VRN
= R
VRP
= Z
0
R
0
= R
VRN
= R
VRP
= Z
0

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English