Xilinx virtex-5 fpga

264 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Differential HSTL Class I (1.8V)
Figure 6-54 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class I (1.8V) with unidirectional termination.
Figure 6-55 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class I (1.8V) with unidirectional DCI termination.
X-Ref Target - Figure 6-54
Figure 6-54: Differential HSTL (1.8V) Class I Unidirectional Termination
X-Ref Target - Figure 6-55
Figure 6-55: Differential HSTL (1.8V) Class I DCI Unidirectional Termination
ug190_6_51_030306
+
–
External Termination
Z
0
IOB
IOB
DIFF_HSTL_I_18
DIFF_HSTL_I_18
Z
0
DIFF_HSTL_I_18
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
ug190_6_52_030306
IOB
DIFF_HSTL_I_DCI_18
DIFF_HSTL_I_DCI_18
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_HSTL_I_DCI_18
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
Z
0
Z
0