Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 121
UG190 (v5.0) June 19, 2009
Additional Block RAM Features in Virtex-5 Devices
Simple Dual-Port Block RAM
Each 18 Kb block and 36 Kb block can also be configured in a simple dual-port RAM mode.
In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM and
72 bits for the 36 Kb block RAM. In simple dual-port mode, independent Read and Write
operations can occur simultaneously, where port A is designated as the Read port and port
B as the Write port. When the Read and Write port access the same data location at the
same time, it is treated as a collision, similar to the port collision in true dual-port mode.
Readback through the configuration port is not supported in simple dual-port block RAM
mode. Figure 4-6 shows the simple dual-port data flow.
X-Ref Target - Figure 4-6
Figure 4-6: Simple Dual-Port Data Flow
Table 4-3: Simple Dual-Port Names and Descriptions
Port Names Descriptions
DO Data Output Bus
DOP Data Output Parity Bus
DI Data Input Bus
DIP Data Input Parity Bus
RDADDR Read Data Address Bus
RDCLK Read Data Clock
RDEN Read Port Enable
REGCE Output Register Clock Enable
SSR Synchronous Set/Reset
WE Byte-wide Write Enable
WRADDR Write Data Address Bus
WRCLK Write Data Clock
WREN Write Port Enable
36 Kb Memory Array
DOP
RDEN
RDADDR
RDCLK
REGCE
SSR
DIP
WEADDR
WE
WRCLK
WREN
DO
DI
ug190_4_02_041206
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8
9
9
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Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English