Xilinx virtex-5 fpga

80 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 2: Clock Management Technology
Clock Switching Between Two DCMs
Figure 2-13 illustrates switching between two clocks from two DCMs while keeping both
DCMs locked.
X-Ref Target - Figure 2-13
Figure 2-13: Clock Switching Between Two DCMs
CLKIN
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
DO(15:0)
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
CLKIN CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
DO(15:0)
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
IBUFG
IBUFG
CLKA
DCM_ADV
DCM_ADV
CLKB
I0
I0
S
BUFGMUX
BUFG
BUFG
ug190_2_14_032506