Xilinx virtex-5 fpga - Chapter 1: Clock Resources

Virtex-5 FPGA User Guide www.xilinx.com 25
UG190 (v5.0) June 19, 2009
Chapter 1
Clock Resources
Global and Regional Clocks
For clocking purposes, each Virtex®-5 device is divided into regions. The number of
regions varies with device size, eight regions in the smallest device to 24 regions in the
largest one. Global I/O and regional clocking resources manage complex and simple
clocking requirements. Non-clock resources, such as local routing, are not recommended
when performing clock functions.
Global Clocks
Each Virtex-5 device has 32 global clock lines that can clock all sequential resources on the
whole device (CLB, block RAM, CMTs, and I/O), and also drive logic signals. Any ten of
these 32 global clock lines can be used in any region. Global clock lines are only driven by
a global clock buffer, which can also be used as a clock enable circuit, or a glitch-free
multiplexer. It can select between two clock sources, and can also switch away from a
failed clock source.
A global clock buffer is often driven by a Clock Management Tile (CMT) to eliminate the
clock distribution delay, or to adjust its delay relative to another clock. There are more
global clocks than CMTs, but a CMT often drives more than one global clock.
Regional Clocks and I/O Clocks
Each region has two regional clock buffers and four regional clock trees. A Virtex-5 I/O
bank spans exactly one region with the exception of some banks in the center column. Each
bank with the size identical to a region contains four clock-capable clock inputs. Each of
these inputs can differentially or single-endedly drive four I/O clocks and two regional
clocks in the same bank or region. In addition, regional clocks can drive regional clock trees
in the adjacent regions. When the clock-capable I/Os are driven by single-ended clocks,
then the clock must be connected to the positive (P) side of the differential “clock capable”
pin pair. The negative (N) side can be used as a general purpose I/O or left unconnected.
The regional clock buffer can be programmed to divide the incoming clock rate by any
integer number from 1 to 8. This feature, in conjunction with the programmable
serializer/deserializer in the IOB, (see Chapter 8, “Advanced SelectIO Logic Resources”),
allows source-synchronous systems to cross clock domains without using additional logic
resources.
A third type of clocking resource, I/O clocks, are very fast and serve localized I/O
serializer/deserializer circuits. See Chapter 8, “Advanced SelectIO Logic Resources.”