Xilinx virtex-5 fpga - Page 257

Virtex-5 FPGA User Guide www.xilinx.com 257
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Figure 6-46 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.5V) with unidirectional DCI termination.
Figure 6-47 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.5V) with bidirectional termination.
X-Ref Target - Figure 6-46
Figure 6-46: Differential HSTL (1.5V) Class II DCI Unidirectional Termination
ug190_6_44_020306
IOB
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_HSTL_II_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
CCO
= 1.5V
Z
0
Z
0
X-Ref Target - Figure 6-47
Figure 6-47: Differential HSTL (1.5V) Class II Bidirectional Termination
Z
0
IOB
IOB
DIFF_HSTL_II DIFF_HSTL_II
+
–
External Termination
V
TT
= 0.75V
50Ω
DIFF_HSTL_II
ug190_6_45_020306
Z
0
DIFF_HSTL_II
DIFF_HSTL_II DIFF_HSTL_II
+
–
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω