Xilinx virtex-5 fpga - Page 153

Virtex-5 FPGA User Guide www.xilinx.com 153
UG190 (v5.0) June 19, 2009
FIFO Timing Models and Parameters
Clock Event 1: Write Operation and Assertion of Almost FULL Signal
During a write operation to an almost full FIFO, the Almost FULL signal is asserted.
• At time T
FDCK_DI
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
inputs of the FIFO.
• At time T
FCCK_WREN
, before clock event 1 (WRCLK), write enable becomes valid at
the WREN input of the FIFO.
• At time T
FCKO_AFULL
, one clock cycle after clock event 1 (WRCLK), Almost Full is
asserted at the AFULL output pin of the FIFO.
Clock Event 2: Write Operation, and Assertion of FULL Signal
The FULL signal pin is asserted when the FIFO is full.
• At time T
FDCK_DI
, before clock event 2 (WRCLK), data 04 becomes valid at the DI
inputs of the FIFO.
• Write enable remains asserted at the WREN input of the FIFO.
• At time T
FCKO_FULL
, after clock event 2 (WRCLK), Full is asserted at the FULL output
pin of the FIFO.
If the FIFO is full, and a read followed by a write is performed, the FULL signal remains
asserted.
Clock Event 3: Write Operation and Assertion of Write Error Signal
The write error signal pin is asserted when data going into the FIFO is not written because
the FIFO is in a Full state.
• At time T
FDCK_DI
, before clock event 3 (WRCLK), data 05 becomes valid at the DI
inputs of the FIFO.
• Write enable remains asserted at the WREN input of the FIFO.
• At time T
FCKO_WRERR
, after clock event 3 (WRCLK), a write error is asserted at the
WRERR output pin of the FIFO. Data 05 is not written into the FIFO.
Clock Event 4: Write Operation and Deassertion of Write Error Signal
The write error signal pin is deasserted when a user stops trying to write into a full FIFO.
• At time T
FCCK_WREN
, before clock event 4 (WRCLK), write enable is deasserted at the
WREN input of the FIFO.
• At time T
FCKO_WRERR
, after clock event 4 (WRCLK), write error is deasserted at the
WRERR output pin of the FIFO.
The write error signal is asserted/deasserted at every write-clock positive edge. As long as
both the write enable and Full signals are true, write error will remain asserted.