Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 209
UG190 (v5.0) June 19, 2009
CLB / Slice Timing Models
Clock Event 1: Shift In
During a write (Shift In) operation, the single-bit content of the register at the address on
the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to
this register is reflected on the A/B/C/D outputs synchronously, if the address is
unchanged during the clock event. If the A/B/C/D inputs are changed during a clock
event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.
• At time T
WS
before clock event 1, the write-enable signal (WE) becomes valid-High,
enabling the SRL for the Write operation that follows.
• At time T
DS
before clock event 1 the data becomes valid (0) at the DI input of the SRL
and is reflected on the A/B/C/D output after a delay of length T
REG
after clock event
1. Since the address 0 is specified at clock event 1, the data on the DI input is reflected
at A/B/C/D output, because it is written to register 0.
Clock Event 2: Shift In
• At time T
DS
before clock event 2, the data becomes valid (1) at the DI input of the SRL
and is reflected on the A/B/C/D output after a delay of length T
REG
after clock event
2. Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
Clock Event 3: Shift In/Addressable (Asynchronous) READ
All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (A/B/C/D outputs) after a delay of length T
ILO
(propagation delay
through a LUT).
• At time T
DS
before clock event 3, the data becomes valid (1) at the DI input of the SRL
and is reflected on the A/B/C/D output T
REG
time after clock event 3.
• The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0
(in this example, this was the first data shifted in), and it is reflected on the A/B/C/D
output after a delay of length T
ILO
.
Clock Event 32: MSB (Most Significant Bit) Changes
At time T
REG
after clock event 32, the first bit shifted into the SRL becomes valid (logical 0
in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is
also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T
REG
and
T
WOSCO
after clock event 1.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English