Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 313
UG190 (v5.0) June 19, 2009
Simultaneous Switching Output Limits
• Maximum allowable power system disturbance voltage (nominal 600 mV)
• Capacitive loading (nominal 10 pF per load)
When the electrical characteristics of a design differ from the nominal values, the system
SSO limit changes. The degree of difference determines the new effective limit for the
design. A figure called “SSO Allowance” is used as a single derating factor, taking into
account the combined effect of all three groups of system electrical characteristics.
The SSO allowance is a number ranging from 0 to 100% and is a product of three scaling
factors:
The First Scaling Factor accounts for the PCB PDS parasitic inductance. It is determined by
dividing the nominal PCB PDS inductance by the user's PCB PDS inductance, L
PDS_USR
.
The PCB PDS inductance is determined based on a set of board geometries: board
thickness, via diameter, breakout trace width and length, and any other additional
structures including sockets.
The Second Scaling Factor accounts for the maximum allowable power system disturbance.
It is determined by dividing the user's maximum allowable power system disturbance,
(V
DISTURBANCE_USER
) by the nominal maximum power system disturbance.
V
DISTURBANCE_USER
is usually determined by taking the lesser of input undershoot
voltage and input logic low threshold.
The Third Scaling Factor accounts for the capacitive loading of outputs driven by the FPGA.
It is based on the transient current impact of every additional picofarad of load capacitance
above the assumed nominal. For every additional 1 pF of load capacitance over the
nominal, approximately 9 mV of additional power system disturbance will occur. The
additional power system disturbance is compared to the nominal power system
disturbance, and a scale factor is derived from the relationship. C
LOAD_USER
is the user's
average load capacitance.
Example calculations show how each scale factor is computed, as well as the SSO
allowance. The system parameters used in this example are:
L
PDS_USER
=1.1nH
V
DISTURBANCE_USER
= 550 mV
C
LOAD_USER
=22pF
First Scaling Factor (SF1) = L
PDS_NOM
/L
PDS_USER
= 1.0 nH/1.1 nH
=0.909
Second Scaling Factor (SF2) = V
DISTURBANCE_USER
/V
DISTURBANCE_NOM
= 550 mV/600 mV
=0.917
Third Scaling Factor (SF3)
=V
DISTURBANCE_NOM
/((C
LOAD_USER
–C
LOAD_NOM
) × 9mV/pF)+ V
DISTURBANCE_NOM
= 600 mV/((22 pF – 15 pF) × 9 mV/pF) + 600 mV
= 600 mV/663 mV
=0.905

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English