Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 343
UG190 (v5.0) June 19, 2009
Input/Output Delay Element (IODELAY)
Instantiating IDELAYCTRL With and Without LOC Constraints
There are cases where the user instantiates an IDELAYCTRL module with a LOC
constraint but also instantiates an IDELAYCTRL module without a LOC constraint. In the
case where an IP Core is instantiated with a non-location constrained IDELAYCTRL
module and also wants to instantiate an IDELAYCTRL module without a LOC constraint
for another part of the design, the implementation tools will perform the following:
• Instantiate the LOC IDELAYCTRL instances as described in the section Instantiating
IDELAYCTRL with Location (LOC) Constraints.
• Replicate the non-location constrained IDELAYCTRL instance to populate with an
IDELAYCTRL instance in every clock region without a location constrained
IDELAYCTRL instance in place.
• The signals connected to the RST and REFCLK input ports of the non-location
constrained IDELAYCTRL instance are connected to the corresponding input ports of
the replicated IDELAYCTRL instances.
• If the RDY port of the non-location constrained IDELAYCTRL instance is ignored,
then all the RDY signals of the replicated IDELAYCTRL instances are also ignored.
• If the RDY port of the non-location constrained IDELAYCTRL instance is connected,
then the RDY port of the non-location constrained instance plus the RDY ports of the
replicated instances are connected to an auto-generated AND gate. The
implementation tools assign the signal name connected to the RDY port of the non-
location constrained instance to the output of the AND gate.
• All the ports of the location constrained instances (RST, REFCLK, and RDY) are
independent from each other and from the replicated instances.
The VHDL and Verilog use models for instantiating a mixed usage model are provided in
the Libraries Guide. In the example, a user is instantiating a non-location constrained
IDELAYCTRL instance with the RDY signal connected. This discussion is also valid when
the RDY signal is ignored.
The circuitry that results from instantiating the IDELAYCTRL components is illustrated in
Figure 7-21.
X-Ref Target - Figure 7-20
Figure 7-20: Instantiate IDELAYCTRL with LOC Constraint
REFCLK RDY
RST
rdy_1
rst_1
rst_2
rst_n
.
.
..
REFCLK
.
.
.
.
..
IDELAYCTRL_1
REFCLK RDY
RST
rdy_2
IDELAYCTRL_2
REFCLK RDY
RST
rdy_n
IDELAYCTRL_n
ug190_7_15_041306

Xilinx virtex-5 fpga Specifications

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Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English