Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 97
UG190 (v5.0) June 19, 2009
General Usage Description
DI[15:0] Input
The dynamic reconfiguration data input (DI) bus provides reconfiguration data.
When not used, all bits must be set to zero.
DWE Input
The dynamic reconfiguration write enable (DWE) input pin provides the write
enable control signal to write the DI data into the DADDR address. When not used,
it must be tied Low.
DEN Input
The dynamic reconfiguration enable (DEN) provides the enable control signal to
access the dynamic reconfiguration feature. When the dynamic reconfiguration
feature is not used, DEN must be tied Low.
DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port.
REL Input
The release pin is used when the PLL is in PMCD mode. When in PLL mode, leave
unconnected or tied Low. Only use this pin when porting existing Virtex-4 designs
containing the legacy PMCD mode.
CLKOUT[0:5]
(1)
Output
User configurable clock outputs (0 through 5) that can be divided versions of the
VCO phase outputs (user controllable) from 1 (bypassed) to 128. The input clock and
output clocks are phase aligned.
CLKFBOUT Output Dedicated PLL feedback output.
CLKOUTDCM[0:5]
(1)
Output
User configurable clocks (0 through 5) that can only connect to the DCM within the
same CMT as the PLL.
CLKFBDCM Output
PLL feedback used to compensate if the PLL is driving the DCM. If the CLKFBOUT
pin is used for this purpose, the software will automatically map to the correct port.
LOCKED Output
An output from the PLL that indicates when the PLL has achieved phase alignment
within a predefined window and frequency matching within a predefined PPM
range. The PLL automatically locks after power on, no extra reset is required.
LOCKED will be deasserted if the input clock stops or the phase alignment is
violated (e.g., input clock phase shift). The PLL must be reset after LOCKED is
deasserted.
DO[15:0] Output
The dynamic reconfiguration output bus provides PLL data output when using
dynamic reconfiguration.
DRDY Output
The dynamic reconfiguration ready output (DRDY) provides the response to the
DEN signal for the PLLs dynamic reconfiguration feature.
Notes:
1. CLKOUT
N
and CLKOUTDCM
N
are utilizing the same output counters and can not be operated independently.
Table 3-3: PLL Ports (Continued)
Pin Name I/O Pin Description

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English