ARM Cortex-M3 User Manual

Exceptions
5-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Note
Entries in Table 5-8 on page 5-21 that are bracketed are optional actions.
Example of reset routine
The reset routine is responsible for starting up the application and then enabling
interrupts. There are three methods for involving the reset ISR after interrupt processing
is performed. This is called the main loop part of the Reset ISR and the three examples
are shown in Example 5-1, Example 5-2 on page 5-23, and Example 5-3 on page 5-23.
Example 5-1 Reset routine with pure sleep on exit (Reset routine does no main
loop work)
void reset()
{
// do setup work (initialize variables, initialize runtime if wanted,
setup peripherals, etc)
nvic[INT_ENA] = 1; // enable interrupts
nvic_regs[NV_SLEEP] |= NVSLEEP_ON_EXIT; // will not normally come back after
1st exception
while (1)
wfi();
}
Setup interrupts Setup priority levels and masks.
Enable interrupts Enable interrupts. Enable the interrupt processing in the NVIC. It is not desirable to have
these occur while they are being enabled. If there are more than 32 interrupts, it takes more
than one Set-Enable Register. PRIMASK can be used through CPS or MSR to mask
interrupts until ready.
[Change Privilege] [Change Privilege]. The Thread mode privilege can be changed to user if required. This
must normally be handled by invoking the SVCall handler.
Loop If sleep-on-exit is enabled, control never returns after the first interrupt/exception is taken.
If sleep-on-exit is selectively enabled/disabled, this loop can manage cleanup and executive
tasks. If sleep-on-exit is not used, the loop is free and can use WFI (sleep-now) when
required.
Table 5-8 Reset boot-up behavior (continued)
Action Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit