ARM Cortex-M3 User Manual

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-23
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Example 5-2 Reset routine with selected Sleep model using WFI
void reset()
{
extern volatile unsigned exc_req;
// do setup work (initialize variables, initialize runtime if wanted,
setup peripherals, etc)
nvic[INT_ENA] = 1; // enable interrupts
while (1)
{
// do some work for (exc_req = FALSE; exc_req == FALSE; )
wfi(); // sleep now - wait for interrupt
// do some post exception checking/cleanup
}
}
Example 5-3 Reset routine with selected Sleep on exit cancelled by ISRs that
require attention
void reset()
{
// do setup work (initialize variables, initialize runtime if wanted,
setup peripherals, etc)
nvic[INT_ENA] = 1; // enable interrupts
while (1)
{
// We are slept until an exception clears sleep on exit state so that we
can post-process/cleanup.
nvic_regs[NV_SLEEP] |= NVSLEEP_ON_EXIT;
while (nvic_regs[NV_SLEEP] & NVSLEEP_ON_EXIT)
wfi(); // sleep now - wait for interrupt which clears
// do some post exception checking/cleanup
}
}
Note
An executive is not required in the Reset routine because an ISR activation can enact
priority level changes. This ensures faster response to changing loads, and uses priority
boosting, to solve priority inversions, to ensure fine grain support. Thread mode is used
for the user code for Real Time Operating System (RTOS) models using threads and
privilege.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit