ARM Cortex-M3 User Manual

List of Tables
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Table 11-33 AHB-AP Debug ROM Address Register bit assignments ..................................... 11-44
Table 11-34 AHB-AP ID Register bit assignments ................................................................... 11-44
Table 12-1 Instruction fetches ................................................................................................... 12-4
Table 12-2 Bus mapper unaligned accesses .......................................................................... 12-11
Table 12-3 Memory attributes ................................................................................................. 12-15
Table 12-4 Interface timing characteristics ............................................................................. 12-16
Table 14-1 ETM core interface inputs and outputs ................................................................... 14-4
Table 14-2 Miscellaneous configuration inputs ......................................................................... 14-4
Table 14-3 Trace port signals ................................................................................................... 14-5
Table 14-4 Other signals ........................................................................................................... 14-5
Table 14-5 Clocks and resets ................................................................................................... 14-6
Table 14-6 APB interface signals .............................................................................................. 14-6
Table 14-7 Cortex-M3 resources .............................................................................................. 14-8
Table 14-8 Exception tracing mapping ................................................................................... 14-13
Table 14-9 ETM registers ....................................................................................................... 14-16
Table 14-10 Boolean function encoding for events ................................................................... 14-22
Table 14-11 Resource identification encoding .......................................................................... 14-23
Table 14-12 Input connections .................................................................................................. 14-23
Table 14-13 Trigger output connections ................................................................................... 14-23
Table 15-1 ETM interface ports ................................................................................................ 15-3
Table 15-2 Branch status signal function .................................................................................. 15-6
Table 15-3 Branches and stages evaluated by the processor .................................................. 15-7
Table 15-4 Example of an opcode sequence ......................................................................... 15-11
Table 16-1 AHB interface ports ................................................................................................. 16-3
Table 17-1 Trace out port signals ............................................................................................. 17-5
Table 17-2 ATB port signals ..................................................................................................... 17-6
Table 17-3 Miscellaneous configuration inputs ......................................................................... 17-6
Table 17-4 APB interface .......................................................................................................... 17-7
Table 17-5 TPIU registers ......................................................................................................... 17-8
Table 17-6 Async Clock Prescaler Register bit assignments ................................................. 17-10
Table 17-7 Selected Pin Protocol Register bit assignments ................................................... 17-11
Table 17-8 Formatter and Flush Status Register bit assignments .......................................... 17-12
Table 17-9 Formatter and Flush Control Register bit assignments ........................................ 17-13
Table 17-10 Integration Test Register-ITATBCTR2 bit assignments ........................................ 17-15
Table 17-11 Integration Test Register-ITATBCTR0 bit assignments ........................................ 17-16
Table 17-12 Integration Mode Control Register bit assignments .............................................. 17-17
Table 17-13 Integration Register : TRIGGER bit assignments ................................................. 17-17
Table 17-14 Integration register : FIFO data 0 bit assignments ................................................ 17-18
Table 17-15 Integration register : FIFO data 1 bit assignments ................................................ 17-19
Table 18-1 Instruction timings ................................................................................................... 18-3
Table 19-1 Miscellaneous input ports timing parameters ......................................................... 19-2
Table 19-2 Low power input ports timing parameters ............................................................... 19-2
Table 19-3 Interrupt input ports timing parameters ................................................................... 19-3
Table 19-4 AHB input ports timing parameters ......................................................................... 19-3
Table 19-5 PPB input port timing parameters ........................................................................... 19-4
Table 19-6 Debug input ports timing parameters ...................................................................... 19-4
Table 19-7 Test input ports timing parameters ......................................................................... 19-5

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit