ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xv
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List of Figures
Cortex-M3 Technical Reference Manual
Key to timing diagram conventions .......................................................................... xxiii
Figure 1-1 Cortex-M3 block diagram .......................................................................................... 1-5
Figure 1-2 Cortex-M3 pipeline stages ...................................................................................... 1-12
Figure 2-1 Processor register set ............................................................................................... 2-4
Figure 2-2 Application Program Status Register bit assignments .............................................. 2-6
Figure 2-3 Interrupt Program Status Register bit assignments .................................................. 2-6
Figure 2-4 Execution Program Status Register .......................................................................... 2-8
Figure 2-5 Little-endian and big-endian memory formats ......................................................... 2-12
Figure 4-1 Processor memory map ............................................................................................ 4-2
Figure 4-2 Bit-band mapping ...................................................................................................... 4-6
Figure 5-1 Stack contents after pre-emption ............................................................................ 5-11
Figure 5-2 Exception entry timing ............................................................................................. 5-13
Figure 5-3 Tail-chaining timing ................................................................................................. 5-14
Figure 5-4 Late-arriving exception timing ................................................................................. 5-15
Figure 5-5 Exception exit timing ............................................................................................... 5-18
Figure 5-6 Interrupt handling flowchart ..................................................................................... 5-34
Figure 5-7 Pre-emption flowchart ............................................................................................. 5-35
Figure 5-8 Return from interrupt flowchart ................................................................................ 5-36
Figure 6-1 Reset signals ............................................................................................................. 6-6
Figure 6-2 Power-on reset .......................................................................................................... 6-6
Figure 6-3 Internal reset synchronization ................................................................................... 6-7
Figure 7-1 SLEEPING power control example ........................................................................... 7-4
Figure 7-2 SLEEPDEEP power control example ........................................................................ 7-5
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