ARM Cortex-M3

List of Figures
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Figure 7-3 WIC mode enable sequence .................................................................................... 7-7
Figure 7-4 Power down timing sequence ................................................................................... 7-8
Figure 7-5 PMU, WIC, and Cortex-M3 interconnect .................................................................. 7-9
Figure 8-1 Interrupt Controller Type Register bit assignments .................................................. 8-7
Figure 8-2 Auxiliary Control Register bit assignments ............................................................... 8-8
Figure 8-3 SysTick Control and Status Register bit assignments .............................................. 8-9
Figure 8-4 SysTick Reload Value Register bit assignments .................................................... 8-11
Figure 8-5 SysTick Current Value Register bit assignments .................................................... 8-11
Figure 8-6 SysTick Calibration Value Register bit assignments .............................................. 8-12
Figure 8-7 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-17
Figure 8-8 CPUID Base Register bit assignments ................................................................... 8-18
Figure 8-9 Interrupt Control State Register bit assignments .................................................... 8-20
Figure 8-10 Vector Table Offset Register bit assignments ........................................................ 8-22
Figure 8-11 Application Interrupt and Reset Control Register bit assignments ......................... 8-23
Figure 8-12 System Control Register bit assignments ............................................................... 8-25
Figure 8-13 Configuration Control Register bit assignments ..................................................... 8-27
Figure 8-14 System Handler Priority Registers bit assignments ................................................ 8-29
Figure 8-15 System Handler Control and State Register bit assignments ................................. 8-30
Figure 8-16 Configurable Fault Status Registers bit assignments ............................................. 8-32
Figure 8-17 Memory Manage Fault Status Register bit assignments ........................................ 8-33
Figure 8-18 Bus Fault Status Register bit assignments ............................................................. 8-34
Figure 8-19 Usage Fault Status Register bit assignments ......................................................... 8-36
Figure 8-20 Hard Fault Status Register bit assignments ........................................................... 8-37
Figure 8-21 Debug Fault Status Register bit assignments ......................................................... 8-39
Figure 8-22 Software Trigger Interrupt Register bit assignments .............................................. 8-42
Figure 9-1 MPU Type Register bit assignments ........................................................................ 9-4
Figure 9-2 MPU Control Register bit assignments ..................................................................... 9-5
Figure 9-3 MPU Region Number Register bit assignments ....................................................... 9-7
Figure 9-4 MPU Region Base Address Register bit assignments .............................................. 9-8
Figure 9-5 MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Figure 10-1 Debug Halting Control and Status Register bit assignments .................................. 10-4
Figure 10-2 Debug Core Register Selector Register bit assignments ....................................... 10-6
Figure 10-3 Debug Exception and Monitor Control Register bit assignments ........................... 10-9
Figure 11-1 System debug access block diagram ..................................................................... 11-4
Figure 11-2 Flash Patch Control Register bit assignments ........................................................ 11-8
Figure 11-3 Flash Patch Remap Register bit assignments ...................................................... 11-10
Figure 11-4 Flash Patch Comparator Registers bit assignments ............................................. 11-11
Figure 11-5 DWT Control Register bit assignments ................................................................. 11-16
Figure 11-6 DWT CPI Count Register bit assignments ............................................................ 11-20
Figure 11-7 DWT Exception Overhead Count Register bit assignments ................................. 11-21
Figure 11-8 DWT Sleep Count Register bit assignments ........................................................ 11-21
Figure 11-9 DWT LSU Count Register bit assignments ........................................................... 11-22
Figure 11-10 DWT Fold Count Register bit assignments ........................................................... 11-23
Figure 11-11 DWT Mask Registers 0-3 bit assignments ............................................................ 11-25
Figure 11-12 DWT Function Registers 0-3 bit assignments ...................................................... 11-26
Figure 11-13 ITM Trace Privilege Register bit assignments ...................................................... 11-33
Figure 11-14 ITM Trace Control Register bit assignments ........................................................ 11-34