List of Figures
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xvii
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Figure 11-15 ITM Integration Write Register bit assignments .................................................... 11-35
Figure 11-16 ITM Integration Read Register bit assignments .................................................... 11-36
Figure 11-17 ITM Integration Mode Control bit assignments ..................................................... 11-37
Figure 11-18 ITM Lock Status Register bit assignments ............................................................ 11-38
Figure 11-19 AHB-AP Control and Status Word Register .......................................................... 11-41
Figure 11-20 AHB-AP ID Register .............................................................................................. 11-44
Figure 12-1 ICode/DCode multiplexer ........................................................................................ 12-9
Figure 14-1 ETM block diagram ................................................................................................. 14-3
Figure 14-2 Return from exception packet encoding ................................................................ 14-12
Figure 14-3 Exception encoding for branch packet .................................................................. 14-14
Figure 15-1 Conditional branch backwards not taken ................................................................ 15-8
Figure 15-2 Conditional branch backwards taken ...................................................................... 15-9
Figure 15-3 Conditional branch forwards not taken .................................................................... 15-9
Figure 15-4 Conditional branch forwards taken .......................................................................... 15-9
Figure 15-5 Unconditional branch without pipeline stalls ......................................................... 15-10
Figure 15-6 Unconditional branch with pipeline stalls .............................................................. 15-10
Figure 15-7 Unconditional branch in execute aligned .............................................................. 15-11
Figure 15-8 Unconditional branch in execute unaligned .......................................................... 15-11
Figure 15-9 Example of an opcode sequence .......................................................................... 15-13
Figure 17-1 TPIU block diagram (non-ETM version) .................................................................. 17-3
Figure 17-2 TPIU block diagram (ETM version) ......................................................................... 17-4
Figure 17-3 Supported Sync Port Size Register bit assignments ............................................. 17-10
Figure 17-4 Async Clock Prescaler Register bit assignments .................................................. 17-10
Figure 17-5 Selected Pin Protocol Register bit assignments ................................................... 17-11
Figure 17-6 Formatter and Flush Status Register bit assignments .......................................... 17-12
Figure 17-7 Formatter and Flush Control Register bit assignments ......................................... 17-13
Figure 17-8 Integration Test Register-ITATBCTR2 bit assignments ........................................ 17-15
Figure 17-9 Integration Test Register-ITATBCTR0 bit assignments ........................................ 17-16
Figure 17-10 Integration Mode Control Register bit assignments .............................................. 17-16
Figure 17-11 Integration Register : TRIGGER bit assignments ................................................. 17-17
Figure 17-12 Integration register : FIFO data 0 bit assignments ................................................ 17-18
Figure 17-13 Integration register : FIFO data 1 bit assignments ................................................ 17-19
Figure 17-14 Dedicated pin used for TRACESWO .................................................................... 17-21
Figure 17-15 SWO shared with TRACEPORT ........................................................................... 17-22
Figure 17-16 SWO shared with JTAG-TDO ............................................................................... 17-22
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