ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-17
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[21] FOLDEVTENA Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows
(every 256 cycles of folded instructions). A folded instruction is one that does not incur
even one cycle to execute. For example, an IT instruction is folded away and so does not
use up one cycle.
1 = Folded instruction count events enabled.
0 = Folded instruction count events disabled.
Reset clears the FOLDEVTENA bit.
[20] LSUEVTENA Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256
cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the
instruction.
1 = LSU count events enabled.
0 = LSU count events disabled.
Reset clears the LSUEVTENA bit.
[19] SLEEPEVTENA Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256
cycles that the processor is sleeping).
1 = Sleep count events enabled.
0 = Sleep count events disabled.
Reset clears the SLEEPEVTENA bit.
[18] EXCEVTENA Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every
256 cycles of interrupt overhead).
1 = Interrupt overhead event enabled.
0 = Interrupt overhead event disabled.
Reset clears the EXCEVTENA bit.
[17] CPIEVTENA Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256
cycles of multi-cycle instructions).
1 = CPI counter events enabled.
0 = CPI counter events disabled.
Reset clears the CPIEVTENA bit.
[16] EXCTRCENA Enables Interrupt event tracing:
1 = interrupt event trace enabled
0 = interrupt event trace disabled.
Reset clears the EXCEVTENA bit.
[15:13] - Reserved
Table 11-7 DWT Control Register bit assignments (continued)
Bits Field Function

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit