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[12] PCSAMPLEENA Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter

triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this

bit overrides CYCEVTENA (bit [20]).

1 = PC Sampling event enabled.

0 = PC Sampling event disabled.

Reset clears the PCSAMPLENA bit.

[11:10] SYNCTAP Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here

picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT

CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and

SYNCENA must be set to 1.

0b00 = Disabled. No synch counting.

0b01 = Tap at CYCCNT bit 24.

0b10 = Tap at CYCCNT bit 26.

0b11 = Tap at CYCCNT bit 28.

[9] CYCTAP Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]:

CYCTAP = 0 selects bit [6] to tap

CYCTAP = 1 selects bit [10] to tap.

When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into

the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit

change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.

[8:5] POSTCNT Post-scalar counter for CYCTAP.

When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is

down-counted when not 0.

If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the

value from POSTPRESET (bits [4:1]).

[4:1] POSTPRESET Reload value for POSTCNT, bits [8:5], post-scalar counter.

If this value is 0, events are triggered on each tap change (a power of 2, such as 1<<6 or

1<<10).

If this field has a non-0 value, this forms a count-down value, to be reloaded into

POSTCNT each time it reaches 0. For example, a value 1 in this register means an event

is formed every other tap change.

[0] CYCCNTENA Enable the CYCCNT counter. If not enabled, the counter does not count and no event is

generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize

the CYCCNT counter to 0.

Table 11-7 DWT Control Register bit assignments (continued)

Bits Field Function

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit