ARM Cortex-M3 User Manual

Programmer’s Model
2-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Compare negation of register value with another register value CMN <Rn>, <Rm>
Compare immediate 8-bit value CMP <Rn>, #<immed_8>
Compare registers CMP <Rn>, <Rm>
Compare high register to low or high register CMP <Rn>, <Rm>
Change processor state CPS <effect>, <iflags>
Copy high or low register value to another high or low register CPY <Rd> <Rm>
Bitwise exclusive OR register values EOR <Rd>, <Rm>
Condition the following instruction
Condition the following two instructions
Condition the following three instructions
Condition the following four instructions
IT <cond>
IT<x> <cond>
IT<x><y> <cond>
IT<x><y><z> <cond>
Multiple sequential memory word loads LDMIA <Rn>!, <registers>
Load memory word from base register address + 5-bit immediate offset LDR <Rd>, [<Rn>, #<immed_5> * 4]
Load memory word from base register address + register offset LDR <Rd>, [<Rn>, <Rm>]
Load memory word from PC address + 8-bit immediate offset LDR <Rd>, [PC, #<immed_8> * 4]
Load memory word from SP address + 8-bit immediate offset LDR, <Rd>, [SP, #<immed_8> * 4]
Load memory byte [7:0] from register address + 5-bit immediate offset LDRB <Rd>, [<Rn>, #<immed_5>]
Load memory byte [7:0] from register address + register offset LDRB <Rd>, [<Rn>, <Rm>]
Load memory halfword [15:0] from register address + 5-bit immediate offset
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
Load halfword [15:0] from register address + register offset LDRH <Rd>, [<Rn>, <Rm>]
Load signed byte [7:0] from register address + register offset LDRSB <Rd>, [<Rn>, <Rm>]
Load signed halfword [15:0] from register address + register offset LDRSH <Rd>, [<Rn>, <Rm>]
Logical shift left by immediate number LSL <Rd>, <Rm>, #<immed_5>
Logical shift left by number in register LSL <Rd>, <Rs>
Logical shift right by immediate number
LSR <Rd>, <Rm>, #<immed_5>
Logical shift right by number in register LSR <Rd>, <Rs>
Table 2-4 16-bit Cortex-M3 instruction summary (continued)
Operation Assembler

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit