ARM Cortex-M3

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-15
Unrestricted Access Non-Confidential
Move immediate 8-bit value to register MOV <Rd>, #<immed_8>
Move low register value to low register MOV <Rd>, <Rn>
Move high or low register value to high or low register MOV <Rd>, <Rm>
Multiply register values MUL <Rd>, <Rm>
Move complement of register value to register MVN <Rd>, <Rm>
Negate register value and store in register NEG <Rd>, <Rm>
No operation NOP <c>
Bitwise logical OR register values ORR <Rd>, <Rm>
Pop registers from stack POP <registers>
Pop registers and PC from stack POP <registers, PC>
Push registers onto stack PUSH <registers>
Push LR and registers onto stack PUSH <registers, LR>
Reverse bytes in word and copy to register REV <Rd>, <Rn>
Reverse bytes in two halfwords and copy to register REV16 <Rd>, <Rn>
Reverse bytes in low halfword [15:0], sign-extend, and copy to register REVSH <Rd>, <Rn>
Rotate right by amount in register ROR <Rd>, <Rs>
Subtract register value and C flag from register value SBC <Rd>, <Rm>
Send event SEV <c>
Store multiple register words to sequential memory locations STMIA <Rn>!, <registers>
Store register word to register address + 5-bit immediate offset STR <Rd>, [<Rn>, #<immed_5> * 4]
Store register word to register address STR <Rd>, [<Rn>, <Rm>]
Store register word to SP address + 8-bit immediate offset STR <Rd>, [SP, #<immed_8> * 4]
Store register byte [7:0] to register address + 5-bit immediate offset STRB <Rd>, [<Rn>, #<immed_5>]
Store register byte [7:0] to register address STRB <Rd>, [<Rn>, <Rm>]
Store register halfword [15:0] to register address + 5-bit immediate offset STRH <Rd>, [<Rn>, #<immed_5> * 2]
Table 2-4 16-bit Cortex-M3 instruction summary (continued)
Operation Assembler