ARM Cortex-M3 User Manual

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-23
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Table branch byte TBB [<Rn>, <Rm>]
Table branch halfword TBH [<Rn>, <Rm>, LSL #1]
Exclusive OR register value with immediate 12-bit value TEQ.W <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register value TEQ.W <Rn>, <Rm>{, <shift}
Logical AND register value with 12-bit immediate value TST.W <Rn>, #<modify_constant(immed_12)>
Logical AND register value with shifted register value TST.W <Rn>, <Rm>{, <shift>}
Copy bit field from register value to register and zero-extend to
32 bits
UBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Unsigned divide UDIV<c> <Rd>,<Rn>,<Rm>
Multiply two unsigned register values and add to a 2-register
value
UMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two unsigned register values UMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Unsigned saturate USAT <c> <Rd>, #<imm>, <Rn>{, <shift>}
Copy unsigned byte to register and zero-extend to 32 bits UXTB.W <Rd>, <Rm>{, <rotation>}
Copy unsigned halfword to register and zero-extend to 32 bits UXTH.W <Rd>, <Rm>{, <rotation>}
Wait for event WFE.W
Wait for interrupt WFI.W
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit