ARM Cortex-M3 User Manual

Programmer’s Model
2-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Register byte [7:0] to register address immediate 8-bit offset,
postindexed
STRB.W <Rxf>, [<Rn>], #+/–<offset_8>
Register byte [7:0] to register address shifted by 0, 1, 2, or 3
places
STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Store doubleword, preindexed STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Store doubleword, postindexed STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]
Store register exclusive calculates an address from a base
register value and an immediate offset, and stores a word from
a register to memory if the executing processor has exclusive
access to the memory addressed.
STREX <c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
Store register exclusive byte derives an address from a base
register value, and stores a byte from a register to memory if
the executing processor has exclusive access to the memory
addressed
STREXB <c> <Rd>,<Rt>,[<Rn>]
Store register exclusive halfword derives an address from a
base register value, and stores a halfword from a register to
memory if the executing processor has exclusive access to the
memory addressed.
STREXH <c> <Rd>,<Rt>,[<Rn>]
Register halfword [15:0] to register address + immediate 12-bit
offset
STRH.W <Rxf>, [<Rn>, #<offset_12>]
Register halfword [15:0] to register address shifted by 0, 1, 2,
or 3 places
STRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register halfword [15:0] to register address immediate 8-bit
offset, preindexed
STRH{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register halfword [15:0] to register address immediate 8-bit
offset, postindexed
STRH.W <Rxf>, [<Rn>], #+/–<offset_8>
Subtract immediate 12-bit value from register value SUB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value from register value SUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value from register value SUBW.W <Rd>, <Rn>, #<immed_12>
Sign extend byte to 32 bits SXTB.W <Rd>, <Rm>{, <rotation>}
Sign extend halfword to 32 bits SXTH.W <Rd>, <Rm>{, <rotation>}
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit