ARM Cortex-M3

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-21
Unrestricted Access Non-Confidential
Reverse bytes in each halfword REV16.W <Rd>, <Rn>
Reverse bytes in bottom halfword and sign-extend REVSH.W <Rd>, <Rn>
Rotate right by number in register ROR{S}.W <Rd>, <Rn>, <Rm>
Rotate right with extend RRX{S}.W <Rd>, <Rm>
Subtract a register value from an immediate 12-bit value RSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract a register value from a shifted register value RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value and C bit from register value
SBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value and C bit from register value SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Copy selected bits to register and sign-extend SBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Signed divide SDIV<c> <Rd>,<Rn>,<Rm>
Send event SEV<c>
Multiply signed words and add signed-extended value to
2-register value
SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two signed register values SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Signed saturate SSAT.W <c> <Rd>, #<imm>, <Rn>{, <shift>}
Multiple register words to consecutive memory locations STM{IA|DB}.W <Rn>{!}, <registers>
Register word to register address + immediate 12-bit offset STR.W <Rxf>, [<Rn>, #<offset_12>]
Register word to register address immediate 8-bit offset,
postindexed
STR.W <Rxf>, [<Rn>], #+/–<offset_8>
Register word to register address shifted by 0, 1, 2, or 3 places STR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register word to register address immediate 8-bit offset,
preindexed Store, preindexed
STR.W <Rxf>, [<Rn>, #+/-<offset_8>]{!}
STRT.W <Rxf>, [<Rn>, #<offset_8>]
Register byte [7:0] to register address immediate 8-bit offset,
preindexed
STRB{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register byte [7:0] to register address + immediate 12-bit
offset
STRB.W <Rxf>, [<Rn>, #<offset_12>]
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler