ARM Cortex-M3 User Manual

Programmer’s Model
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Memory signed halfword [15:0] from base register address
immediate 8-bit offset, preindexed
LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>] !
Memory signed halfword [15:0] from register address shifted
left by 0, 1, 2, or 3 places
LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed halfword from PC address immediate 12-bit
offset
LDRSH.W <Rxf>, [PC, #+/–<offset_12>]
Logical shift left register value by number in register LSL{S}.W <Rd>, <Rn>, <Rm>
Logical shift right register value by number in register LSR{S}.W <Rd>, <Rn>, <Rm>
Multiply two signed or unsigned register values and add the
low 32 bits to a register value
MLA.W <Rd>, <Rn>, <Rm>, <Racc>
Multiply two signed or unsigned register values and subtract
the low 32 bits from a register value
MLS.W <Rd>, <Rn>, <Rm>, <Racc>
Move immediate 12-bit value to register MOV{S}.W <Rd>, #<modify_constant(immed_12)>
Move shifted register value to register MOV{S}.W <Rd>, <Rm>{, <shift>}
Move immediate 16-bit value to top halfword [31:16] of
register
MOVT.W <Rd>, #<immed_16>
Move immediate 16-bit value to bottom halfword [15:0] of
register and clear top halfword [31:16]
MOVW.W <Rd>, #<immed_16>
Move to register from status MRS<c> <Rd>, <psr>
Move to status register MSR<c> <psr>_<fields>,<Rn>
Multiply two signed or unsigned register values MUL.W <Rd>, <Rn>, <Rm>
No operation NOP.W
Logical OR NOT register value with immediate 12-bit value ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR NOT register value with shifted register value ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Logical OR register value with immediate 12-bit value ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR register value with shifted register value ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Reverse bit order RBIT.W <Rd>, <Rm>
Reverse bytes in word REV.W <Rd>, <Rm>
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit