Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-19
Unrestricted Access Non-Confidential
Load register exclusive calculates an address from a base
register value and an immediate offset, loads a word from
memory, writes it to a register
LDREX<c> <Rt>,[<Rn>{,#<imm>}]
Load register exclusive halfword calculates an address from a
base register value and an immediate offset, loads a halfword
from memory, writes it to a register
LDREXH<c> <Rt>,[<Rn>{,#<imm>}]
Load register exclusive byte calculates an address from a base
register value and an immediate offset, loads a byte from
memory, writes it to a register
LDREXB<c> <Rt>,[<Rn>{,#<imm>}]
Memory halfword [15:0] from base register address +
immediate 12-bit offset
LDRH.W <Rxf>, [<Rn>, #<offset_12>]
Memory halfword [15:0] from base register address immediate
8-bit offset, preindexed
LDRH.W <Rxf>, [<Rn>, #<+/–<offset_8>]
!
Memory halfword [15:0] from base register address immediate
8-bit offset, postindexed
LDRH.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory halfword [15:0] from register address shifted left by
0, 1, 2, or 3 places
LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory halfword from PC address immediate 12-bit offset
LDRH.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed byte [7:0] from base register address +
immediate 12-bit offset
LDRSB.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed byte [7:0] from base register address
immediate 8-bit offset, postindexed
LDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory signed byte [7:0] from base register address
immediate 8-bit offset, preindexed
LDRSB.W <Rxf>, [<Rn>, #<+/–<offset_8>]
!
Memory signed byte [7:0] from register address shifted left by
0, 1, 2, or 3 places
LDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed byte from PC address immediate 12-bit offset
LDRSB.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed halfword [15:0] from base register address +
immediate 12-bit offset
LDRSH.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed halfword [15:0] from base register address
immediate 8-bit offset, postindexed
LDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler
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