ARM Cortex-M3 - Page 66

Programmer’s Model
2-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Memory word from base register address + immediate 12-bit
offset
LDR.W <Rxf>, [<Rn>, #<offset_12>]
Memory word to PC from register address + immediate 12-bit
offset
LDR.W PC, [<Rn>, #<offset_12>]
Memory word to PC from base register address immediate
8-bit offset, postindexed
LDR.W PC, [Rn], #<+/-<offset_8>
Memory word from base register address immediate 8-bit
offset, postindexed
LDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Memory word from base register address immediate 8-bit
offset, preindexed
LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
LDRT.W <Rxf>, [<Rn>, #<offset_8>]
Memory word to PC from base register address immediate
8-bit offset, preindexed
LDR.W PC, [<Rn>, #+/–<offset_8>]!
Memory word from register address shifted left by 0, 1, 2, or 3
places
LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word to PC from register address shifted left by 0, 1,
2, or 3 places
LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word from PC address immediate 12-bit offset LDR.W <Rxf>, [PC, #+/–<offset_12>]
Memory word to PC from PC address immediate 12-bit offset LDR.W PC, [PC, #+/–<offset_12>]
Memory byte [7:0] from base register address + immediate
12-bit offset
LDRB.W <Rxf>, [<Rn>, #<offset_12>]
Memory byte [7:0] from base register address immediate 8-bit
offset, postindexed
LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory byte [7:0] from register address shifted left by 0, 1, 2,
or 3 places
LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory byte [7:0] from base register address immediate 8-bit
offset, preindexed
LDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>] !
Memory byte from PC address immediate 12-bit offset
LDRB.W <Rxf>, [PC, #+/–<offset_12>]
Memory doubleword from register address 8-bit offset 4,
preindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Memory doubleword from register address 8-bit offset 4,
postindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler