ARM Cortex-M3 User Manual

Programmer’s Model
2-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Memory word from base register address + immediate 12-bit
offset
LDR.W <Rxf>, [<Rn>, #<offset_12>]
Memory word to PC from register address + immediate 12-bit
offset
LDR.W PC, [<Rn>, #<offset_12>]
Memory word to PC from base register address immediate
8-bit offset, postindexed
LDR.W PC, [Rn], #<+/-<offset_8>
Memory word from base register address immediate 8-bit
offset, postindexed
LDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Memory word from base register address immediate 8-bit
offset, preindexed
LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
LDRT.W <Rxf>, [<Rn>, #<offset_8>]
Memory word to PC from base register address immediate
8-bit offset, preindexed
LDR.W PC, [<Rn>, #+/–<offset_8>]!
Memory word from register address shifted left by 0, 1, 2, or 3
places
LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word to PC from register address shifted left by 0, 1,
2, or 3 places
LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word from PC address immediate 12-bit offset LDR.W <Rxf>, [PC, #+/–<offset_12>]
Memory word to PC from PC address immediate 12-bit offset LDR.W PC, [PC, #+/–<offset_12>]
Memory byte [7:0] from base register address + immediate
12-bit offset
LDRB.W <Rxf>, [<Rn>, #<offset_12>]
Memory byte [7:0] from base register address immediate 8-bit
offset, postindexed
LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory byte [7:0] from register address shifted left by 0, 1, 2,
or 3 places
LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory byte [7:0] from base register address immediate 8-bit
offset, preindexed
LDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>] !
Memory byte from PC address immediate 12-bit offset
LDRB.W <Rxf>, [PC, #+/–<offset_12>]
Memory doubleword from register address 8-bit offset 4,
preindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Memory doubleword from register address 8-bit offset 4,
postindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit