ARM Cortex-M3

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-17
Unrestricted Access Non-Confidential
Conditional branch B{cond}.W <label>
Clear bit field BFC.W <Rd>, #<lsb>, #<width>
Insert bit field from one register value into another BFI.W <Rd>, <Rn>, #<lsb>, #<width>
Bitwise AND register value with complement of immediate
12-bit value
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Bitwise AND register value with complement of shifted
register value
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Branch with link BL <label>
Branch with link (immediate) BL<c> <label>
Unconditional branch B.W <label>
Clear exclusive clears the local record of the executing
processor that an address has had a request for an exclusive
access.
CLREX <c>
Return number of leading zeros in register value CLZ.W <Rd>, <Rn>
Compare register value with two’s complement of immediate
12-bit value
CMN.W <Rn>, #<modify_constant(immed_12)>
Compare register value with two’s complement of shifted
register value
CMN.W <Rn>, <Rm>{, <shift>}
Compare register value with immediate 12-bit value CMP.W <Rn>, #<modify_constant(immed_12)>
Compare register value with shifted register value CMP.W <Rn>, <Rm>{, <shift>}
Data memory barrier DMB <c>
Data synchronization barrier DSB <c>
Exclusive OR register value with immediate 12-bit value EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register value EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Instruction synchronization barrier ISB <c>
Load multiple memory registers, increment after or decrement
before
LDM{IA|DB}.W <Rn>{!}, <registers>
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Operation Assembler