Xilinx virtex-5 fpga - Page 311

Virtex-5 FPGA User Guide www.xilinx.com 311
UG190 (v5.0) June 19, 2009
Simultaneous Switching Output Limits
3.3V LVCMOS33_2_slow 20 40
LVCMOS33_4_slow 20 40
LVCMOS33_6_slow 20 40
LVCMOS33_8_slow 20 40
LVCMOS33_12_slow 20 40
LVCMOS33_16_slow 20 40
LVCMOS33_24_slow 20 40
LVCMOS33_2_fast 20 40
LVCMOS33_4_fast 20 40
LVCMOS33_6_fast 20 40
LVCMOS33_8_fast 20 40
LVCMOS33_12_fast 20 40
LVCMOS33_16_fast 20 40
LVCMOS33_24_fast 15 30
LVTTL_2_slow 20 40
LVTTL_4_slow 20 40
LVTTL_6_slow 20 40
LVTTL_8_slow 20 40
LVTTL_12_slow 20 40
LVTTL_16_slow 20 40
LVTTL_24_slow 20 40
LVTTL_2_fast 20 40
LVTTL_4_fast 20 40
LVTTL_6_fast 20 40
LVTTL_8_fast 20 40
LVTTL_12_fast 20 40
LVTTL_16_fast 20 40
LVTTL_24_fast 15 30
PCI33_3 20 40
PCI66_3 20 40
PCIX 20 40
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage IOSTANDARD Limit per 20-pin Bank Limit per 40-pin Bank