Xilinx virtex-5 fpga

310 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
2.5V LVCMOS25_2_slow 20 40
LVCMOS25_4_slow 20 40
LVCMOS25_6_slow 20 40
LVCMOS25_8_slow 20 40
LVCMOS25_12_slow 20 40
LVCMOS25_16_slow 20 40
LVCMOS25_24_slow 20 40
LVCMOS25_2_fast 20 40
LVCMOS25_4_fast 20 40
LVCMOS25_6_fast 20 40
LVCMOS25_8_fast 20 40
LVCMOS25_12_fast 20 40
LVCMOS25_16_fast 20 40
LVCMOS25_24_fast 15 30
LVDCI_25 50 Ω 20 40
SSTL2_I 20 40
SSTL2_I_DCI 20 40
SSTL2_II 20 40
SSTL2_II_DCI 20 40
HSLVDCI_25 50 Ω 20 40
DIFF_SSTL_I 20 40
DIFF_SSTL_I_DCI 20 40
DIFF_SSTL_II 20 40
DIFF_SSTL_II_DCI 20 40
LVPECL_25 20 40
BLVDS_25 20 40
LVDS_25 20 40
LVDSEXT_25 20 40
RSDS_25 20 40
HT_25 20 40
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage IOSTANDARD Limit per 20-pin Bank Limit per 40-pin Bank