Xilinx virtex-5 fpga - Page 309

Virtex-5 FPGA User Guide www.xilinx.com 309
UG190 (v5.0) June 19, 2009
Simultaneous Switching Output Limits
1.8V LVCMOS18_2_slow 20 40
LVCMOS18_4_slow 20 40
LVCMOS18_6_slow 20 40
LVCMOS18_8_slow 20 40
LVCMOS18_12_slow 20 40
LVCMOS18_16_slow 20 40
LVCMOS18_2_fast 20 40
LVCMOS18_4_fast 20 40
LVCMOS18_6_fast 20 40
LVCMOS18_8_fast 20 40
LVCMOS18_12_fast 20 40
LVCMOS18_16_fast 20 40
LVDCI_18 50 Ω 20 40
HSTL_I_18 20 40
HSTL_I_DCI_18 20 40
HSTL_II_18 20 40
HSTL_II_DCI_18 20 40
HSTL_III_18 17 35
HSTL_III_DCI_18 17 35
HSTL_IV_18 10 20
HSTL_IV_DCI_18 10 20
SSTL18_I 20 40
SSTL18_I_DCI 20 40
SSTL18_II 20 40
SSTL18_II_DCI 20 40
HSLVDCI_18 50 Ω 20 40
DIFF_HSTL_I_18 20 40
DIFF_HSTL_I_DCI_18 20 40
DIFF_HSTL_II_18 20 40
DIFF_HSTL_II_DCI_18 20 40
DIFF_SSTL18_I 20 40
DIFF_SSTL18_I_DCI 20 40
DIFF_SSTL18_II 20 40
DIFF_SSTL18_II_DCI 20 40
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage IOSTANDARD Limit per 20-pin Bank Limit per 40-pin Bank