Xilinx virtex-5 fpga - Page 333

Virtex-5 FPGA User Guide www.xilinx.com 333
UG190 (v5.0) June 19, 2009
Input/Output Delay Element (IODELAY)
IODELAY #(
.DELAY_SRC ("IO"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (12),
.ODELAY_VALUE (12),
.REFCLK_FREQUENCY (200.0)
)IODELAY_INST (
.C(1'b0),
.CE(1'b0),
.DATAIN(1'b0),
.IDATAIN(IDATAIN),
.INC(1'b0),
.ODATAIN(ODATAIN),
.RST(1'b0),
.T(TSCONTROL),
.DATAOUT(DATAOUT)
);
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("SYNC")
)ODDR_INST (
.C(clk),
.CE(1'b1),
.D1(D1),
.D2(D2),
.R(1'b0),
.S(1'b0),
.Q(ODATAIN)
);
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("SYNC")
)TRI_ODDR_INST (
.C(clk),
.CE(1'b1),
.D1(T1),
.D2(T2),
.R(1'b0),
.S(1'b0),
.Q(TSCONTROL)
);
IDELAYCTRL IDELAYCTRL_INST (
.REFCLK(refclk),
.RST(RST),
.RDY()
);