Xilinx virtex-5 fpga

182 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-6
Figure 5-6: Distributed RAM (RAM32X2Q)
UG190_5_06_032706
DI1 DOD[0]
DOC[0]
DOD[1]
DOC[1]
DOB[0]
DOB[1]
DOA[0]
DOA[1]
DI2
DID[1]
DID[0]
ADDRD[4:0]
ADDRC[4:0]
ADDRB[4:0]
ADDRA[4:0]
WCLK
WED
(CLK)
(WE)
5
5
DPRAM32
RAM 32X2Q
A[6:1]
WA[6:1]
CLK
WE
O6
O5
DI1
DI2
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DI2
DI2
B[5:1]
C[5:1]
D[5:1]
(AI/BI/CI/DI)
(DX)
A[5:1]
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
O5
O5
O5