Xilinx virtex-5 fpga - Page 183

Virtex-5 FPGA User Guide www.xilinx.com 183
UG190 (v5.0) June 19, 2009
CLB Overview
X-Ref Target - Figure 5-7
Figure 5-7: Distributed RAM (RAM32X6SDP)
UG190_5_06_032706
DI1
O[1]
O[2]
O[3]
O[4]
O[5]
O[6]
DI2
unused
unused
WADDR[5:1]
WADDR[6] = 1
RADDR[5:1]
RADDR[6] = 1
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
WCLK
WED
(CLK)
(WE)
5
5
DPRAM32
RAM 32X6SDP
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DI2
DI2
B[5:1]
C[5:1]
D[5:1]
A[5:1]
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
O5
O5
O5