Xilinx virtex-5 fpga

184 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 64 x 4-bit single-port distributed RAM.
If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a
SLICEM, as long as they share the same clock, write enable, and shared read and write port
address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM.
X-Ref Target - Figure 5-8
Figure 5-8: Distributed RAM (RAM64X1S)
X-Ref Target - Figure 5-9
Figure 5-9: Distributed RAM (RAM64X1D)
ug190_5_07_032706
Output
Registered
Output
(Optional)
DI1
DQ
(DX)
D
A[5:0]
WCLK
WE
(D[6:1])
(CLK)
(WE/CE)
6
SPRAM64
RAM64X1S
A[6:1]
WA[6:1]
CLK
WE
O6
O
6
UG190_5_09_050506
DI1
(DX)
D
A[5:0]
WCLK
WE
(D[6:1])
(CLK)
(WE/CE)
6
6
DPRAM64
RAM64X1D
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRA[5:0]
(C[6:1])
6
6
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
Registered
Output
(Optional)
DQ
SPO
Registered
Output
(Optional)
DQ
DPO