Name: Xilinx virtex-5 fpga
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Virtex-5 FPGA User Guide www.xilinx.com 185

UG190 (v5.0) June 19, 2009

CLB Overview

X-Ref Target - Figure 5-10

Figure 5-10: Distributed RAM (RAM64X1Q)

ug190_5_10_032706

DI1

DID

ADDRD

ADDRC

ADDRB

ADDRA

WCLK

(CLK)

(WE)

DPRAM64

RAM64X1Q

A[6:1]

WA[6:1]

CLK

DI1

DPRAM64

A[6:1]

WA[6:1]

CLK

DI1

(B[6:1])

(C[6:1])

(D[6:1])

(DX)

(A[6:1])

DPRAM64

A[6:1]

WA[6:1]

CLK

DI1

DPRAM64

A[6:1]

WA[6:1]

CLK

Registered

Output

DOD

DOC

DOB

DOA

(Optional)

Registered

Output

(Optional)

Registered

Output

(Optional)

Registered

Output

(Optional)

Default Chapter3
- Revision History3
  - Table of Contents9
Preface: about this Guide21
Chapter 1: Clock Resources25
Chapter 2: Clock Management Technology47
Chapter 3: Phase-Locked Loops (Plls)89
Chapter 4: Block RAM113
Chapter 5: Configurable Logic Blocks (Clbs)173
Chapter 6: Selectio Resources217
Chapter 7: Selectio Logic Resources317
Chapter 8 : Advanced Selectio Logic Resources353
Index383

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English

Xilinx virtex-5 fpga User Manual

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