Xilinx virtex-5 fpga - Page 185

Virtex-5 FPGA User Guide www.xilinx.com 185
UG190 (v5.0) June 19, 2009
CLB Overview
X-Ref Target - Figure 5-10
Figure 5-10: Distributed RAM (RAM64X1Q)
ug190_5_10_032706
DI1
DID
ADDRD
ADDRC
ADDRB
ADDRA
WCLK
WE
(CLK)
(WE)
DPRAM64
RAM64X1Q
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
(B[6:1])
(C[6:1])
(D[6:1])
(DX)
(A[6:1])
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
Registered
Output
DOD
DOC
DOB
DOA
(Optional)
DQ
Registered
Output
(Optional)
DQ
Registered
Output
(Optional)
DQ
Registered
Output
(Optional)
DQ