Xilinx virtex-5 fpga

188 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-13
Figure 5-13: Distributed RAM (RAM128X1D)
UG190_5_13_050506
DI1
D
DX
AX
A[6:0]
WCLK
DPRA[6:0]
WE
(CLK)
(WE)
7
DPRAM64
RAM128X1D
A[6:1]
WA[7:1]
CLK
WE
O6
DI1
6
7
DPRAM64
A[6:1]
WA[7:1]
CLK
WE
O6
Registered
Output
F7BMUX
(Optional)
DQ
SPO
DI1
6
7
DPRAM64
A[6:1]
WA[7:1]
CLK
WE
O6
DI1
6
7
DPRAM64
A[6:1]
WA[7:1]
CLK
WE
O6
Registered
Output
F7AMUX
(Optional)
DQ
DPO
A6 (CX)
6