Xilinx virtex-5 fpga - Page 193

Virtex-5 FPGA User Guide www.xilinx.com 193
UG190 (v5.0) June 19, 2009
CLB Overview
X-Ref Target - Figure 5-19
Figure 5-19: 96-bit Shift Register Configuration
UG190_c5_19_020909
DI1
SHIFTIN (D)
A[6:0]
CLK
WE
AX (A5)
(CLK)
(WE/CE)
5
SRL32
A[6:2]
CLK
WE
O6
MC31
MC31
DI1
5
SRL32
A[6:2]
CLK
WE
O6
F7BMUX
Not Used
F8MUX
Registered
Output
Output (Q)
(Optional)
DQ
(BQ)
(BMUX)
DI1
5
SRL32
A[6:2]
CLK
WE
O6
F7AMUX
CX (A5)
BX (A6)