Xilinx virtex-5 fpga User Manual

282 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Figure 6-73 shows a sample circuit illustrating a valid termination technique for
differential SSTL2 Class II (2.5V) with unidirectional DCI termination.
Figure 6-74 shows a sample circuit illustrating a valid termination technique for
differential SSTL2 Class II (2.5V) with bidirectional termination.
X-Ref Target - Figure 6-73
Figure 6-73: Differential SSTL2 (2.5V) Class II Unidirectional DCI Termination
ug190_6_69_030506
IOB
DIFF_SSTL2_II_DCI
DIFF_SSTL2_II_DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_SSTL2_II_DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
CCO
= 2.5V
Z
0
Z
0
R
0
= 25Ω
R
0
= 25Ω
X-Ref Target - Figure 6-74
Figure 6-74: Differential SSTL2 (2.5V) Class II with Bidirectional Termination
Z
0
IOB
IOB
DIFF_SSTL2_II DIFF_SSTL2_II
+
–
External Termination
V
TT
= 1.25V
DIFF_SSTL2_II
ug190_6_70_071707
Z
0
DIFF_SSTL2_II
DIFF_SSTL2_II DIFF_SSTL2_II
+
–
V
TT
= 1.25V
50Ω
50Ω
V
TT
= 1.25V
V
TT
= 1.25V
50Ω
25Ω
25Ω
25Ω
25Ω
50Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English