Xilinx virtex-5 fpga

300 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
HSTL_III_18 1.8 Note (2) 1.08 N/R N/R
HSTL_IV_18 1.08 N/R N/R
HSTL_I_18 0.9 N/R N/R
HSTL_II_18 0.9 N/R N/R
DIFF_HSTL_I_18 N/R N/R N/R
DIFF_HSTL_II_18 N/R N/R N/R
SSTL18_I 0.9 N/R N/R
SSTL18_II 0.9 N/R N/R
DIFF_SSTL18_I N/R N/R N/R
DIFF_SSTL18_II N/R N/R N/R
LVCMOS18 1.8 N/R N/R N/R
LVDCI_18 N/R Series N/R
HSLVDCI_18 V
CCO
/2 Series N/R
LVDCI_DV2_18 N/R Series N/R
HSTL_III_DCI_18 1.08 N/R Single
HSTL_IV_DCI_18 1.08 Single Single
HSTL_I_DCI_18 0.9 N/R Split
HSTL_II_DCI_18 0.9 Split Split
HSTL_II_T_DCI_18 0.9 N/R Split
DIFF_HSTL_I_DCI_18 N/R N/R Split
DIFF_HSTL_II_DCI_18 N/R Split Split
SSTL18_I_DCI 0.9 N/R Split
SSTL18_II_DCI 0.9 Split Split
SSTL18_II_T_DCI 0.9 N/R Split
DIFF_SSTL18_I_DCI N/R N/R Split
DIFF_SSTL18_II_DCI N/R Split Split
Table 6-39: I/O Compatibility (Continued)
I/O Standard
V
CCO
V
REF
Termination Type
Output Input Input Output Input