Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 69
UG190 (v5.0) June 19, 2009
DCM Design Guidelines
In the FIXED, VARIABLE_POSITIVE, and VARIABLE_CENTER phase-shift mode, the
PHASE_SHIFT attribute is in the numerator of the following equation.
Phase Shift (ns) = (PHASE_SHIFT/256) × PERIOD
CLKIN
Where PERIOD
CLKIN
denotes the effective CLKIN frequency.
In VARIABLE_CENTER and FIXED modes, the full range of the PHASE_SHIFT attribute is
always –255 to +255. In the VARIABLE_POSITIVE mode, the range of the PHASE_SHIFT
attribute is 0 to +255.
In the DIRECT phase-shift mode, the PHASE_SHIFT attribute is the multiplication factor
in the following equation:
Phase Shift (ns) = PHASE_SHIFT × DCM_TAP
In DIRECT modes, the full range of the PHASE_SHIFT attribute is 0 to 1023.
FINE_SHIFT_RANGE represents the total delay achievable by the phase-shift delay line.
Total delay is a function of the number of delay taps used in the circuit. The absolute range
is specified in the DCM Timing Parameters section of the Virtex-5 FPGA Data Sheet across
process, voltage, and temperature. The different absolute ranges are outlined in this
section.
The fixed mode allows the DCM to insert a delay line in the CLKFB or the CLKIN path.
This gives access to the +FINE_SHIFT_RANGE when the PHASE_SHIFT attribute is set to
a positive value, and –FINE_SHIFT_RANGE when the PHASE_SHIFT attribute is set to a
negative value.
Absolute Range (Variable-Center Mode) = ± FINE_SHIFT_RANGE ÷ 2
The variable-center mode allows symmetric, dynamic sweeps from –255/256 to +255/256,
by having the DCM set the zero-phase-skew point in the middle of the delay line. This
divides the total delay-line range in half.
Absolute Range (Fixed) = ± FINE_SHIFT_RANGE
In the fixed mode, a phase shift is set during configuration in the range of –255/256 to
+255/256.
Absolute Range (Variable-Positive and Direct Modes) = + FINE_SHIFT_RANGE
In the variable-positive and direct modes, the phase-shift only operates in the positive
range. The DCM sets the zero-phase-skew point at the beginning of the delay line. This
produces a full delay line in one direction.
Both the PHASE_SHIFT attribute and the FINE_SHIFT_RANGE parameter need to be
considered to determine the limiting range of each application. The “Phase-Shift
Examples” section illustrates possible scenarios.
In variable and direct mode, the PHASE_SHIFT value can dynamically increment or
decrement as determined by PSINCDEC synchronously to PSCLK, when the PSEN input
is active.
Phase-Shift Examples
The following usage examples take both the PHASE_SHIFT attribute and
FINE_SHIFT_RANGE into consideration:
• If PERIODCLKIN = 2 × FINE_SHIFT_RANGE, then the PHASE_SHIFT in fixed
mode is limited to ±128. In variable-positive mode, PHASE_SHIFT is limited to +128.
In variable-center mode the PHASE_SHIFT is limited to ±64.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English