ARM Cortex-M3 User Manual

Clocking and Resets
6-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
The nTRST signal must be asserted with regard to the SWCLKTCK clock because the
SWJ-DP performs no synchronization.
6.3.4 SW-DP reset
SW-DP is reset with DBGRESETn. This reset must be synchronized to DBGCLK.
6.3.5 Normal operation
During normal operation, neither processor reset nor power-on reset is asserted. If the
SWJ-DP port is not being used, the value of nTRST does not matter.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit