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Chapter 11

System Debug

This chapter describes the processor system debug. It contains the following sections:

• About system debug on page 11-2

• System debug access on page 11-3

• System debug programmer’s model on page 11-5

• FPB on page 11-6

• DWT on page 11-13

• ITM on page 11-30

• AHB-AP on page 11-39.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit