ARM Cortex-M3 User Manual

Preface
xxiv Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Prefix P Denotes Advanced Peripheral Bus (APB) signals.
Prefix R Denotes AXI read data channel signals.
Prefix W Denotes AXI write data channel signals.
Further reading
This section lists publications by ARM and by third parties.
See
http://infocenter.arm.com for access to ARM documentation.
ARM publications
This book contains information that is specific to this product. See the following
documents for other relevant information:
• ARMv7-M Architecture Reference Manual (ARM DDI 0403)
• ARM AMBA
®
3 AHB-Lite Protocol (v1.0) (ARM IHI 0033)
• ARM CoreSight
™
Components Technical Reference Manual (ARM DDI 0314)
• ARM Debug Interface v5, Architecture Specification (ARM IHI 0031)
• ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0014).
Other publications
This section lists relevant documents published by third parties:
• IEEE Standard Test Access Port and Boundary-Scan Architecture 1149.1-2001
(JTAG).

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit