ARM Cortex-M3 User Manual

Bus Interface
12-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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12.5.5 Memory attributes
The processor exports memory attributes on the System bus by using a sideband bus
called MEMATTRS. For more information, see Memory attributes on page 12-15.
12.5.6 Pipelined instruction fetches
To provide a clean timing interface on the System bus, instruction and vector fetch
requests to this bus are registered. This results in an additional cycle of latency because
instructions fetched from the System bus take two cycles. This also means that
back-to-back instruction fetches from the System bus are not possible.
Note
Instruction fetch requests to the ICode bus are not registered. Performance critical code
must run from the ICode interface.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit