ARM Cortex-M3 User Manual

Introduction
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• Bit-banding. The bus matrix converts bit-band alias accesses into bit-band region
accesses. It performs:
— bit field extract for bit-band loads
— atomic read-modify-write for bit-band stores.
• Write buffering. The bus matrix contains a one-entry write buffer to decouple bus
stalls from the processor core.
Chapter 12 Bus Interface describes the bus interfaces.
1.2.4 FPB
You can configure the implementation to include an FPB. The FPB implements
hardware breakpoints, and patches accesses from code space to system space. If present,
you can configure the FPB to:
• contain six instruction comparators for instruction and literal matching in
addition to flash patching. These comparators either remap instruction fetches
from code space to system space, or perform a hardware breakpoint.
• contain two comparators that can be used for breakpoints only. These
comparators can remap literal accesses from code space to system space.
Chapter 11 System Debug describes the FPB.
1.2.5 DWT
You can configure the implementation to include a DWT. If present, you can configure
the DWT to incorporate the following debug functionality:
• four comparators that you can configure either as a hardware watchpoint, an ETM
trigger, a PC sampler event trigger, or a data address sampler event trigger
• several counters or a data match event trigger for performance profiling
• configurable to emit PC samples at defined intervals, and to emit interrupt event
information.
Chapter 11 System Debug describes the DWT.
1.2.6 ITM
You can configure the implementation to contain an ITM. The ITM is a an application
driven trace source that supports application event trace and printf style debugging.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit