ARM Cortex-M3 User Manual

Trace Port Interface Unit
17-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
The width (n) of this register can be determined from reading the Claim Tag Set
Register.
Read Current Claim Tag Value
Write Each bit is considered separately:
0 = no effect
1 = clear this bit in the claim tag.
Claim Tag Set Register
The register address, access type, and Reset state are:
Address
0xE0040FA0
Access Read/write
Reset state
0x0
This register forms one half of the Claim Tag value. This location enables individual bits
to be set, write, and returns the number of bits that can be set, read.
Read Each bit is considered separately:
0 = this claim tag bit is not implemented
1 = this claim tag bit is implemented.
Write Each bit is considered separately:
0 = no effect
1 = set this bit in the claim tag.
Device ID Register
The register address, access type, and Reset state are:
Address
0xE0040FC8
Access Read only
Reset state
0xCA0/0xCA1
This register returns:
•
0xCA0 if there is no ETM present.
•
0xCA1 if there is no ETM present.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit