Instruction Timing
18-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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• STR with register offset cannot be pipelined after. STR can only be pipelined
when after an LDR, but nothing can be pipelined after the store. Even a stalled
STR normally only take two cycles, because of the store buffer (bit band, data
segment, and unaligned).
• LDREX and STREX can be pipelined exactly as LDR. Because STREX is treated
more like an LDR, it can be pipelined as explained for LDR. Equally LDREX is
treated exactly as an LDR and so can be pipelined.
• LDRD, STRD cannot be pipelined with preceding or following instructions.
However, the two words are pipelined together. So, three cycles when not stalled.
• LDM, STM cannot be pipelined with preceding or following instructions.
However, all elements after the first are pipelined together. So, a three element
LDM takes 2+1+1 or 5 cycles when not stalled. Similarly, an eight element store
takes nine cycles when not stalled. When interrupted, LDM and STM instructions
continue from where left off when returned to. The continue operation adds one
or two cycles to the first element to get started.
• Unaligned Word or Halfword Loads or stores add penalty cycles. A byte aligned
halfword load or store adds one extra cycle to perform the operation as two bytes.
A halfword aligned word load or store adds one extra cycle to perform the
operation as two halfwords. A byte-aligned word load or store adds two extra
cycles to perform the operation as a byte, a halfword, and a byte. These numbers
increase if the memory stalls. A STR or STRH cannot delay the processor because
of the store buffer.
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