ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Glossary-1
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Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort A mechanism that indicates to a core that the attempted memory access is invalid or not
allowed or that the data returned by the memory access is invalid. An abort can be
caused by the external or internal memory system as a result of attempting to access
invalid or protected instruction or data memory.
See also Data Abort, External Abort and Prefetch Abort.
Addressing modes Various mechanisms, shared by many different instructions, for generating values used
by the instructions.
Advanced High-performance Bus (AHB)
A bus protocol with a fixed pipeline between address/control and data phases. It only
supports a subset of the functionality provided by the AMBA AXI protocol. The full
AMBA AHB protocol specification includes a number of features that are not
commonly required for master and slave IP developments and ARM recommends only
a subset of the protocol is usually used. This subset is defined as the AMBA AHB-Lite
protocol.
See also Advanced Microcontroller Bus Architecture and AHB-Lite.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit